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Move to a High-Level Synthesis Flow to Remain Competitive

In the world of IC design, the RTL flow prevails. But today’s competitive market for state-of-the-art image processing, high-bandwidth communication, and computer vision and neural computing solutions demand another level of abstraction. RTL design and verification does not allow companies in these markets to be competitive as this flow takes too long to get to market.

The only way to target many potential implementation solutions and make last-minute specification changes while staying on schedule successfully is by moving up to an high-level synthesis flow using C++ and/or SystemC.